A Hardware Perspective to Evaluating Probabilistic Circuits

Jelin Leslin, Antti Hyttinen, Karthekeyan Periasamy, Lingyun Yao, Martin Trapp, Martin Andraud
Proceedings of The 11th International Conference on Probabilistic Graphical Models, PMLR 186:349-360, 2022.

Abstract

The always-increasing development of AI-enhanced Internet-of-Things devices has recently pushed the need for on-device computation of AI models. As these tasks require mak- ing robust predictions under uncertainty, probabilistic (graphical) models have recently gained interest also for these applications. However, embedded computation requires high computational efficiency (i.e., high speed and low power) through hardware acceleration. Although the acceleration of deep learning models has shown extensive benefits, this has not translated to probabilistic models as of yet. Probabilistic circuits (PCs), a family of tractable probabilistic models, allow a direct hardware view as they are represented in the form of a computational graph. Over the years, various approaches for structure learning of PCs have been proposed, however, without consideration of their potential hardware cost. In this work, we propose to take a hardware perspective in the evaluation of PC structures. We compare several structure learning strategies, associating each PC with hardware costs (computation power, speed, efficiency), and evaluate which one leads to more hardware- friendly implementations. Our results show that models imposing additional structural constraints on the PC are competitive models in terms of performance while being gen- erally more hardware-efficient, making them suitable candidates for energy-constrained applications.

Cite this Paper

BibTeX
@InProceedings{pmlr-v186-leslin22a, title = {A Hardware Perspective to Evaluating Probabilistic Circuits}, author = {Leslin, Jelin and Hyttinen, Antti and Periasamy, Karthekeyan and Yao, Lingyun and Trapp, Martin and Andraud, Martin}, booktitle = {Proceedings of The 11th International Conference on Probabilistic Graphical Models}, pages = {349--360}, year = {2022}, editor = {Salmerón, Antonio and Rumı́, Rafael}, volume = {186}, series = {Proceedings of Machine Learning Research}, month = {05--07 Oct}, publisher = {PMLR}, pdf = {https://proceedings.mlr.press/v186/leslin22a/leslin22a.pdf}, url = {https://proceedings.mlr.press/v186/leslin22a.html}, abstract = {The always-increasing development of AI-enhanced Internet-of-Things devices has recently pushed the need for on-device computation of AI models. As these tasks require mak- ing robust predictions under uncertainty, probabilistic (graphical) models have recently gained interest also for these applications. However, embedded computation requires high computational efficiency (i.e., high speed and low power) through hardware acceleration. Although the acceleration of deep learning models has shown extensive benefits, this has not translated to probabilistic models as of yet. Probabilistic circuits (PCs), a family of tractable probabilistic models, allow a direct hardware view as they are represented in the form of a computational graph. Over the years, various approaches for structure learning of PCs have been proposed, however, without consideration of their potential hardware cost. In this work, we propose to take a hardware perspective in the evaluation of PC structures. We compare several structure learning strategies, associating each PC with hardware costs (computation power, speed, efficiency), and evaluate which one leads to more hardware- friendly implementations. Our results show that models imposing additional structural constraints on the PC are competitive models in terms of performance while being gen- erally more hardware-efficient, making them suitable candidates for energy-constrained applications.} }
Endnote
%0 Conference Paper %T A Hardware Perspective to Evaluating Probabilistic Circuits %A Jelin Leslin %A Antti Hyttinen %A Karthekeyan Periasamy %A Lingyun Yao %A Martin Trapp %A Martin Andraud %B Proceedings of The 11th International Conference on Probabilistic Graphical Models %C Proceedings of Machine Learning Research %D 2022 %E Antonio Salmerón %E Rafael Rumı́ %F pmlr-v186-leslin22a %I PMLR %P 349--360 %U https://proceedings.mlr.press/v186/leslin22a.html %V 186 %X The always-increasing development of AI-enhanced Internet-of-Things devices has recently pushed the need for on-device computation of AI models. As these tasks require mak- ing robust predictions under uncertainty, probabilistic (graphical) models have recently gained interest also for these applications. However, embedded computation requires high computational efficiency (i.e., high speed and low power) through hardware acceleration. Although the acceleration of deep learning models has shown extensive benefits, this has not translated to probabilistic models as of yet. Probabilistic circuits (PCs), a family of tractable probabilistic models, allow a direct hardware view as they are represented in the form of a computational graph. Over the years, various approaches for structure learning of PCs have been proposed, however, without consideration of their potential hardware cost. In this work, we propose to take a hardware perspective in the evaluation of PC structures. We compare several structure learning strategies, associating each PC with hardware costs (computation power, speed, efficiency), and evaluate which one leads to more hardware- friendly implementations. Our results show that models imposing additional structural constraints on the PC are competitive models in terms of performance while being gen- erally more hardware-efficient, making them suitable candidates for energy-constrained applications.
APA
Leslin, J., Hyttinen, A., Periasamy, K., Yao, L., Trapp, M. & Andraud, M.. (2022). A Hardware Perspective to Evaluating Probabilistic Circuits. Proceedings of The 11th International Conference on Probabilistic Graphical Models, in Proceedings of Machine Learning Research 186:349-360 Available from https://proceedings.mlr.press/v186/leslin22a.html.

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