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Selective Indicator Elimination in Arithmetic Circuits for Bipartite Noisy-OR Bayesian Networks
Proceedings of the 13th International Conference on Probabilistic Graphical Models, PMLR 343:140-152, 2026.
Abstract
Bipartite noisy-OR Bayesian networks (BN2Os) have been compiled into arithmetic circuits (ACs) for exact inference, where evaluation traditionally consists of assigning indicator values at the circuit leaves and propagating values upward to the root. We introduce selective indicator elimination (SIE), a transformation for compiled BN2O ACs that removes indicator-controlled single-variable subcircuits and replaces them with cached values. The resulting method has two phases: an offline transformation phase that prunes such subcircuits and precomputes their replacement values, and an online evaluation phase that parses a query, assigns the appropriate cached values, and propagates over the transformed AC. Unlike prior AC compression methods that simplify static numeric computation by compressing arithmetic subcircuits consisting of multiplication and addition nodes, our approach is the first to eliminate indicator leaves together with their associated indicator-controlled computation while preserving support for general exact inference queries. We formally prove that SIE preserves exact inference correctness. Statistically significant improvements in both circuit size and exact inference runtime are empirically observed for $58%$ of the tested synthetic BN2Os.